1. Field of the Invention
The present invention relates to a device for displaying images. More particularly, the present invention relates to a transistor capable of reducing a parasitic capacitance, and a display device having the transistor.
2. Description of the Related Art
A liquid crystal display (LCD) device employs a gate driver integrated circuit (IC). The gate driver IC is formed, for example, through a tape carrier package (TCP), chip on glass (COG), etc.
Recently, in order to reduce manufacturing cost, a gate-IC-less structure has been developed. According to an LCD device employing the gate IC-less structure, while no gate driver IC is employed, an amorphous silicon thin film transistor (a-Si TFT) performs as the gate driver IC.
An a-Si TFT is disclosed in U.S. Pat. No. 5,517,542 and Korean Patent Laid Open Publication No. 2002-66962.
In the above Korean Patent Laid Open Publication No. 2002-66962, a shift register employing only seven a-Si TFT's and wirings connected to the shift register are disclosed.
FIG. 1 is a circuit diagram illustrating a unit stage of a conventional shift register. The unit stage and the conventional shift register are disclosed in Korean Patent Laid Open Publication No. 2002-66962.
Referring to FIG. 1, each stage of a shift register includes a pull up section 110, a pull down section 120, a pull up driving section 130 and a pull down driving section 140. Each stage outputs a gate signal (or scan signal), based on a scan start signal STV or an output signal of a previous stage. In detail, a first stage outputs a first gate signal based on the scan start signal STV provided from a timing control section (not shown). A second stage outputs a second gate signal based on the first gate signal outputted from the first stage. In other words, an (n+1)-th stage outputs an (n+1)-th gate signal based on an n-th gate signal outputted from an n-th stage, wherein ‘n’ is a natural number.
FIG. 2 is a block diagram illustrating a gate driver circuit including the conventional shift register in FIG. 1.
Referring to FIGS. 1 and 2, a gate driver circuit 174 includes ‘N’stages outputting ‘N’ of gate signals (GOUT1, GOUT2, . . . , GOUTN), respectively.
A first stage receives a scan start signal STV, a gate on voltage VDD, a gate off voltage VSS and a first clock signal CKV and outputs a first gate signal GOUT1 for selecting a first gate line. The scan start signal STV, the gate on voltage VDD and the gate off voltage VSS are provided from a timing control section (not shown). The first gate signal GOUT1 is applied to a second stage.
The second stage receives the first gate signal GOUT1, the gate on voltage VDD, the gate off voltage VSS and a second clock signal CKVB, and outputs a second gate signal GOUT2 for selecting a second gate line. The second gate signal GOUT2 is applied to a third stage.
As described above, an N-th stage receives an (N−1)-th gate signal GOUTN−1 provided from an (N−1)-th stage, the gate on voltage VDD, the gate off voltage VSS and the second clock signal CKVB and outputs an N-th gate signal GOUTN for selecting N-th gate line. The N-th gate signal GOUTN is applied to an (N+1)-th stage.
FIG. 3A is a circuit diagram illustrating a unit stage in the conventional shift register in FIG. 1. FIG. 3B is a timing diagram illustrating an operation of the unit stage in FIG. 3A. FIG. 3C is a circuit diagram illustrating a pull down transistor sampling out a first clock signal in FIG. 3A.
Referring to FIGS. 1 through 3C, a unit stage is formed by one S/R latch 21 and one AND-gate 22. The unit stage operates as shown in FIG. 3B.
The S/R latch 21 may include various embodiments but the S/R latch 21 requires a pull down transistor shown in FIG. 3C for sampling a clock signal CK1 by a signal Q outputted from the S/R latch 21.
An NMOS transistor Q1 in the pull up section 110 corresponds to an a-Si TFT. Consequently, the NMOS transistor Q1 has a relatively lower electron mobility. A gate pulse, in a range of about 20V to about −14V, is applied to drive an LCD device having a relatively large size. Increasing a size of the NMOS transistor Q2 is therefore required in order to drive the LCD device.
Particularly, in the case of an LCD device having 12.1 inches (or 30.734 cm) and XGA resolution, a parasitic capacitance of one gate line ranges from about 250 pF to about 300 pF. In order to use a-Si TFT to drive the gate line, a channel width W of at least about 5500 μm is required when a channel length L is about 4 μm, this channel length being an established minimum design rule.
As a result, a parasitic capacitance Cgd between a gate electrode and a drain electrode of the NMOS TFT Q1 increases. The parasitic capacitance Cgd operates as a coupling capacitance between the gate and drain electrodes. The parasitic capacitance Cgd is electrically coupled to the first or second clock CKV or CKVB that is in a range of about 20V to about −14V. If the parasitic capacitance Cgd reaches about 3 pF, a gate driver circuit malfunctions. When a device to maintain gate off voltage VOFF is not provided, since, so that, a voltage of a gate electrode of the pull up transistor Q1 becomes first or second clock CKV or CKVB, ranging from about 20V to about −14V. Output voltage of the pull up transistor Q1 then reaches about 20V-Vth, wherein Vth corresponds to a threshold voltage. As a result, the output voltage of about 20V-Vth is applied to the gate line causing the gate line to malfunction.
Therefore, for the pull up transistor Q1 to have gate off voltage VOFF, a hold transistor Q5 and a pull down transistor Q2 are formed. The hold transistor Q5 corresponds to an a-Si TFT and is sufficiently large to maintain gate off voltage VOFF. The pull down transistor Q2 pulls down a scan pulse to be the gate off voltage VOFF, after the pull up transistor Q1 is operated.
Due to the relatively big size of the transistors Q1 and Q5, forming the gate driver circuit in a black matrix region or a sealing region presents some difficulty. Furthermore, the hold transistor Q5 may deteriorate, inducing malfunction of the LCD device.